From 4a57fcdc5359584c368d58845e5b55b602a99e67 Mon Sep 17 00:00:00 2001
From: P. J. McDermott <pehjota>
Date: Sun, 08 Jul 2012 19:29:06 -0400
Subject: Add Intel P6 and more information.

---
diff --git a/dev/ports/hardware.mdwn b/dev/ports/hardware.mdwn
index 614d83a..4b8134a 100644
--- a/dev/ports/hardware.mdwn
+++ b/dev/ports/hardware.mdwn
@@ -1,7 +1,7 @@
 [[!meta title="Hardware Ports"]]
 
-ARM ISAs
-========
+ARM
+===
 
 ARM Cortex-A8 Core
 ------------------
@@ -10,75 +10,130 @@ ARM Cortex-A8 Core
     String: cortexa8
     ISAs: ARMv7-A, Thumb, Thumb-2, NEON SIMD
     Word size: 32 bits
+    Address size: 32 bits
     Byte order: little-endian
     PCS: Procedure Call Standard for the ARM Architecture
     Floating-point ABI: hardware
+    GCC CPU name: cortex-a8
     CFLAGS: -O3 -fsingle-precision-constant
     GCC configure options: --with-arch=armv7-a --with-cpu=cortex-a8
      --with-tune=cortex-a8 --with-mode=thumb --with-fpu=neon --with-float=hard
      --with-abi=aapcs-linux
 
 
-Intel ISAs
-==========
+Intel
+=====
 
-Intel486 Microarchitecture
+Intel 80486 Microprocessor
 --------------------------
 
     Status: Potential
     String: i486
     Word size: 32 bits
+    Address size: 32 bits
     Byte order: little-endian
     GCC CPU name: i486
 
+See also:
+
+  * [Information on Intel 80486][intel-80486]
+
 Intel P5 Microarchitecture
 --------------------------
 
     Status: Potential
     String: p5 or i586
     Word size: 32 bits
+    Address size: 32 bits
     Byte order: little-endian
     GCC CPU name: pentium
 
+P5, Intel's first superscalar microarchitecture, was first implemented in
+Pentium CPUs.
+
+See also:
+
+  * [Information on Intel P5][intel-p5]
+
 Intel P5 Microarchitecture + MMX
 --------------------------------
 
     Status: Potential
     String: p5mmx or i586mmx
     Word size: 32 bits
+    Address size: 32 bits
     Byte order: little-endian
     GCC CPU name: pentium-mmx
 
+Intel P6 Microarchitecture
+--------------------------
+
+    Status: Planned
+    String: p6 or i686
+    Word size: 32 bits
+    Address size: 36 bits (PAE)
+    Byte order: little-endian
+    GCC CPU name: pentiumpro
+
+Intel P6 was first implemented in Pentium Pro CPUs and was later revived in
+Pentium M CPUs.
+
+See also:
+
+  * [Information on Intel P6][intel-p6]
+  * [Information on Intel Pentium Pro][intel-pentium-pro]
+
 Intel Core Microarchitecture
 ----------------------------
 
     Status: Planned
     String: core2 or core
     Word size: 64 bits
+    Address size: 64 bits
     Byte order: little-endian
     GCC CPU name: core2
 
+See also:
+
+  * [Information on Intel Core][intel-core]
+
 Intel Nehalem Microarchitecture
 -------------------------------
 
     Status: Potential
     String: nehalem or corei3 or corei7
     Word size: 64 bits
+    Address size: 64 bits
     Byte order: little-endian
     GCC CPU name: corei7
 
+This is the microarchitecture used by CPUs in the first-generation Intel Core
+i7 family.
+
+See also:
+
+  * [Information on Intel Nehalem][intel-nehalem]
+
 Intel Sandy Bridge Microarchitecture
 ------------------------------------
 
     Status: Potential
     String: sandybridge or cori3avx or corei7avx
     Word size: 64 bits
+    Address size: 64 bits
     Byte order: little-endian
     GCC CPU name: corei7-avx
 
+This is the microarchitecture used by CPUs in the second-generation Intel Core
+i7 family.  Sandy Bridge CPUs include an on-die GPU.
+
+See also:
+
+  * [Information on Intel Sandy Bridge][intel-sandybridge]
+
 
-AMD ISAs
-========
+AMD
+===
 
 AMD K8 Microarchitecture
 ------------------------
@@ -86,14 +141,38 @@ AMD K8 Microarchitecture
     Status: Planned
     String: k8
     Word size: 64 bits
+    Address size: 64 bits
     Byte order: little-endian
     GCC CPU name: k8
 
+This is the first implementation of the AMD64 design, a 64-bit extension to the
+IA-32 series.
+
+See also:
+
+  * [Information on AMD K8][amd-k8]
+
 AMD Family 10h Microarchitecture
 --------------------------------
 
     Status: Potential
     String: amdfam10h or fam10h
     Word size: 64 bits
+    Address size: 64 bits
     Byte order: little-endian
     GCC CPU name: amdfam10h
+
+See also:
+
+  * [Information on AMD Family 10h][amd-fam10h]
+
+
+[intel-80486]: https://en.wikipedia.org/wiki/Intel_80486
+[intel-p5]: https://en.wikipedia.org/wiki/P5_%28microarchitecture%29
+[intel-p6]: https://en.wikipedia.org/wiki/P6_%28microarchitecture%29
+[intel-pentium-pro]: https://en.wikipedia.org/wiki/Pentium_Pro
+[intel-core]: https://en.wikipedia.org/wiki/Intel_Core_%28microarchitecture%29
+[intel-nehalem]: https://en.wikipedia.org/wiki/Nehalem_%28microarchitecture%29
+[intel-sandybridge]: https://en.wikipedia.org/wiki/Sandy_Bridge
+[amd-k8]: https://en.wikipedia.org/wiki/AMD_K8
+[amd-fam10h]: https://en.wikipedia.org/wiki/AMD_10h
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