From 200d9e16bec62d0ad84836debcb14875bd2aa7ac Mon Sep 17 00:00:00 2001 From: P. J. McDermott Date: Sun, 08 Jul 2012 16:16:39 -0400 Subject: Add notes regarding architecture ports. --- (limited to 'dev/ports') diff --git a/dev/ports/hardware.mdwn b/dev/ports/hardware.mdwn new file mode 100644 index 0000000..455d672 --- /dev/null +++ b/dev/ports/hardware.mdwn @@ -0,0 +1,99 @@ +[[!meta title="Hardware Ports"]] + +ARM ISAs +======== + +ARM Cortex-A8 Core +------------------ + + Status: Current + String: cortexa8 + ISAs: ARMv7-A, Thumb, Thumb-2, NEON SIMD + Word size: 32 bits + Byte order: little-endian + ABI: GNU EABI + Floating-point ABI: hardware + CFLAGS: -O3 -fsingle-precision-constant + GCC configure options: --with-arch=armv7-a --with-cpu=cortex-a8 + --with-tune=cortex-a8 --with-mode=thumb --with-fpu=neon --with-float=hard + --with-abi=aapcs-linux + + +Intel ISAs +========== + +Intel486 Microarchitecture +-------------------------- + + Status: Potential + String: i486 + Word size: 32 bits + Byte order: little-endian + GCC CPU name: i486 + +Intel P5 Microarchitecture +-------------------------- + + Status: Potential + String: p5 or i586 + Word size: 32 bits + Byte order: little-endian + GCC CPU name: pentium + +Intel P5 Microarchitecture + MMX +-------------------------------- + + Status: Potential + String: p5mmx or i586mmx + Word size: 32 bits + Byte order: little-endian + GCC CPU name: pentium-mmx + +Intel Core Microarchitecture +---------------------------- + + Status: Planned + String: core2 or core + Word size: 64 bits + Byte order: little-endian + GCC CPU name: core2 + +Intel Nehalem Microarchitecture +------------------------------- + + Status: Potential + String: nehalem or corei3 or corei7 + Word size: 64 bits + Byte order: little-endian + GCC CPU name: corei7 + +Intel Sandy Bridge Microarchitecture +------------------------------------ + + Status: Potential + String: sandybridge or cori3avx or corei7avx + Word size: 64 bits + Byte order: little-endian + GCC CPU name: corei7-avx + + +AMD ISAs +======== + +AMD K8 Microarchitecture +------------------------ + + Status: Planned + String: k8 + Word size: 64 bits + Byte order: little-endian + GCC CPU name: k8 + +AMD Family 10h Microarchitecture +-------------------------------- + + Status: Potential + String: amdfam10h or fam10h + Word size: 64 bits + Byte order: little-endian + GCC CPU name: amdfam10h diff --git a/dev/ports/kernels.mdwn b/dev/ports/kernels.mdwn new file mode 100644 index 0000000..bd465a9 --- /dev/null +++ b/dev/ports/kernels.mdwn @@ -0,0 +1,19 @@ +[[!meta title="Kernel Ports"]] + +Linux-libre +=========== + + Status: Current + String: linux + +kFreeBSD +======== + + Status: Potential + String: kfreebsd + +kNetBSD +======= + + Status: Potential + String: knetbsd diff --git a/dev/ports/libraries.mdwn b/dev/ports/libraries.mdwn new file mode 100644 index 0000000..22fb666 --- /dev/null +++ b/dev/ports/libraries.mdwn @@ -0,0 +1,15 @@ +[[!meta title="Library Ports"]] + +EGLIBC +====== + + Status: Current + String: eglibc + +uClibc +====== + +NB: different configurations of uClibc can be ABI-incompatible and should have +their own architecture components. + + Status: Planned -- cgit v0.9.1