Add notes regarding architecture ports.

4 files changed, 141 insertions, 0 deletions

diff --git a/dev/ports.mdwn b/dev/ports.mdwn
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+[[!meta title="Architecture Ports"]]
+
+Following the [Architecture String Syntax specification][arch-string], there are
+three components to any architecture port:
+
+  * The [[hardware|ports/hardware]],
+  * The [[kernel|ports/kernels]], and
+  * The [[system_libraries|ports/libraries]].
diff --git a/dev/ports/hardware.mdwn b/dev/ports/hardware.mdwn
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+[[!meta title="Hardware Ports"]]
+
+ARM ISAs
+========
+
+ARM Cortex-A8 Core
+------------------
+
+    Status: Current
+    String: cortexa8
+    ISAs: ARMv7-A, Thumb, Thumb-2, NEON SIMD
+    Word size: 32 bits
+    Byte order: little-endian
+    ABI: GNU EABI
+    Floating-point ABI: hardware
+    CFLAGS: -O3 -fsingle-precision-constant
+    GCC configure options: --with-arch=armv7-a --with-cpu=cortex-a8
+     --with-tune=cortex-a8 --with-mode=thumb --with-fpu=neon --with-float=hard
+     --with-abi=aapcs-linux
+
+
+Intel ISAs
+==========
+
+Intel486 Microarchitecture
+--------------------------
+
+    Status: Potential
+    String: i486
+    Word size: 32 bits
+    Byte order: little-endian
+    GCC CPU name: i486
+
+Intel P5 Microarchitecture
+--------------------------
+
+    Status: Potential
+    String: p5 or i586
+    Word size: 32 bits
+    Byte order: little-endian
+    GCC CPU name: pentium
+
+Intel P5 Microarchitecture + MMX
+--------------------------------
+
+    Status: Potential
+    String: p5mmx or i586mmx
+    Word size: 32 bits
+    Byte order: little-endian
+    GCC CPU name: pentium-mmx
+
+Intel Core Microarchitecture
+----------------------------
+
+    Status: Planned
+    String: core2 or core
+    Word size: 64 bits
+    Byte order: little-endian
+    GCC CPU name: core2
+
+Intel Nehalem Microarchitecture
+-------------------------------
+
+    Status: Potential
+    String: nehalem or corei3 or corei7
+    Word size: 64 bits
+    Byte order: little-endian
+    GCC CPU name: corei7
+
+Intel Sandy Bridge Microarchitecture
+------------------------------------
+
+    Status: Potential
+    String: sandybridge or cori3avx or corei7avx
+    Word size: 64 bits
+    Byte order: little-endian
+    GCC CPU name: corei7-avx
+
+
+AMD ISAs
+========
+
+AMD K8 Microarchitecture
+------------------------
+
+    Status: Planned
+    String: k8
+    Word size: 64 bits
+    Byte order: little-endian
+    GCC CPU name: k8
+
+AMD Family 10h Microarchitecture
+--------------------------------
+
+    Status: Potential
+    String: amdfam10h or fam10h
+    Word size: 64 bits
+    Byte order: little-endian
+    GCC CPU name: amdfam10h
diff --git a/dev/ports/kernels.mdwn b/dev/ports/kernels.mdwn
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+[[!meta title="Kernel Ports"]]
+
+Linux-libre
+===========
+
+    Status: Current
+    String: linux
+
+kFreeBSD
+========
+
+    Status: Potential
+    String: kfreebsd
+
+kNetBSD
+=======
+
+    Status: Potential
+    String: knetbsd
diff --git a/dev/ports/libraries.mdwn b/dev/ports/libraries.mdwn
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+[[!meta title="Library Ports"]]
+
+EGLIBC
+======
+
+    Status: Current
+    String: eglibc
+
+uClibc
+======
+
+NB: different configurations of uClibc can be ABI-incompatible and should have
+their own architecture components.
+
+    Status: Planned